Method to improve transistor tox using si recessing with no additional masking steps

ABSTRACT

A method of forming a transistor device is provided wherein a gate structure is formed over a semiconductor body of a first conductivity type. The gate structure is formed comprising a protective cap thereover and defining source/drain regions laterally adjacent thereto. A first implant is performed of a second conductivity type into both the gate structure and the source/drain regions. The semiconductor body is etched to form recesses substantially aligned to the gate structure wherein the first implant is removed from the source/drain regions. Source/drain regions are implanted or grown by a selective epitaxial growth.

CROSS-REFERENCE TO RELATED APPLICATIONS

This Application is a continuation of U.S. application Ser. No.11/868,787 filed on Oct. 8, 2007, entitled A Method To ImproveTransistor Tox Using Si Recessing With No Additional Masking Steps,commonly assigned with the present invention and incorporated herein byreference.

FIELD OF THE INVENTION

The present invention relates to various methods for the manufacture oftransistor devices to improve poly depletion and oxide thickness.

BACKGROUND OF THE INVENTION

Field effect transistors (FETs) are widely used in the electronicsindustry for switching, amplification, filtering, and other tasksrelated to both analog and digital electrical signals. Most common amongthese are metal-oxide-semiconductor field-effect transistors (MOSFETs),wherein a gate electrode is energized to create an electric field in achannel region of a semiconductor body, by which electrons are allowedto travel through the channel between a source region and a drain regionof the semiconductor body. The source and drain regions are typicallyformed by adding dopants to targeted regions on either side of thechannel. A gate dielectric or gate oxide is formed over the channel, anda gate electrode or gate contact is formed over the gate dielectric. Thegate dielectric and gate electrode layers are then patterned to form agate structure overlying the channel region of the substrate.

Conventionally, upon patterning a polysilicon gate electrode, the dopingof the polysilicon is performed concurrently with the formation of thesource/drains on opposing sides of the gate electrode in thesemiconductor body. Typically, heavy doping at this stage is desirablein order to avoid poly depletion and thus keep oxide thickness (Tox) assmall as possible. However, too much doping in the source/drain regionscan lead to overrun of the extension regions, and lead undesirably topunchthrough and/or leakage.

The necessity to control Short Channel Effects (SCE) requires thecomplete suppression of dopant diffusion in order to control the lateraland vertical depth and the abruptness of the junction profile. It isknown that junctions formed by Solid Phase Epitaxial Regrowth (SPER) ofa doped amorphous region allow for meta-stable high activation level andperfectly abrupt profiles. The excellent abruptness of SPER junctionresults from a poor activation level in the crystalline Si below theamorphous region. Despite the excellent vertical junction profile,several integration issues rise from the lateral amorphisation and fromthe End of Range (EOR) defects. A strong dependence is often observed ofthe lateral amorphous region profile near the gate on the implantationsused in the prior art. Unless optimized this leads to poor doping activeconcentration under the gate that significantly increases the overlapresistance. Through a SPER extension process, species combinations ofGe, BF2 and B for PMOS, and As for NMOS have been characterized fortransistor performance. Under the correct conditions, the transistorperformance can be recovered. An optimised SPER junction can preservethe oxide integrity and avoid the degradation of the poly.

Accordingly, there is a need for improved transistor fabrication methodsfor processing by which the benefits of decoupling the conventionaltradeoff between oxide integrity and degradation of the poly can beachieved while avoiding or mitigating the problems encountered inconventional techniques.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basicunderstanding of one or more aspects of the disclosure. This summary isnot an extensive overview of the invention, and is neither intended toidentify key or critical elements of the invention, nor to delineate thescope thereof. Rather, the primary purpose of the summary is to presentsome concepts of the invention in a simplified form as a prelude to themore detailed description that is presented later.

In accordance with one aspect of the disclosure, a method of forming atransistor device is provided wherein a gate structure is formed over asemiconductor body of a first conductivity type. The gate structure isformed comprising a protective cap thereover and defining source/drainregions laterally adjacent thereto. A first implant is performed of asecond conductivity type into both the gate structure and thesource/drain regions. In one example, the semiconductor body is etchedto form recesses substantially aligned to the gate structure wherein thefirst implant is substantially removed from the source/drain regions. Inanother example, the semiconductor body is etched to form recessessubstantially aligned to the gate structure wherein the first implant isentirely removed from the source/drain regions. In one example, suchrecesses are formed immediately after gate patterning or after formationof offset spacers (used for extension region implants) on lateral edgesof the gate. The protective cap is removed and a second implant of asecond conductivity type is performed into the source/drain regions andthe gate structure.

In another aspect of the disclosure, a method of forming a transistordevice is provided wherein a gate structure is formed over asemiconductor body of a first conductivity type. The gate structure isformed comprising a protective cap thereover and defining source/drainregions laterally adjacent thereto. A source/drain implant of a secondconductivity type is then performed into both the gate structure andsource/drain regions. In one example, the semiconductor body is etchedto form recesses substantially aligned to the gate structure wherein thefirst source/drain implant is substantially removed therefrom. Inanother example, the semiconductor body is etched to form recessessubstantially aligned to the gate structure wherein the first implant isentirely removed from the source/drain regions. In one example, suchrecesses are formed immediately after gate patterning or after formationof offset spacers (used for extension region implants) on lateral edgesof the gate. The recesses are then filled with silicon germanium via aselective epitaxial deposition process. The silicon germanium materialhas a different lattice spacing than the silicon channel, therebyimparting a compressive strain to the channel region under the gate.

In one example, the silicon germanium material is doped with boronin-situ for the formation of p-type extension regions. In anotherexample, an extension region implant is performed into the silicongermanium material after the selective epi deposition, followed by theformation of sidewall spacers and source/drain implants. Having theboron doped silicon germanium material (either doped in-situ or viaimplantation) close to the gate as opposed to laterally spaced away(e.g., at the source/drain locations) advantageously allows lessgermanium to be employed in the recesses for a given desired stress,thereby reducing threading dislocation defects.

In yet another embodiment, the disclosure is directed to a method offorming an NMOS and a PMOS transistor concurrently, comprising forming agate structure with a protective cap over a semiconductor body in anNMOS region and a PMOS region, respectively. In addition, the methodcomprises performing an implant of n-type source and drain regions intothe NMOS region, p-type source and drain regions into the PMOS region ofthe semiconductor body, and implanting into the gate structure. Etchinginto the semiconductor body is performed in both the NMOS and PMOSregions to form recesses substantially aligned to the gate structurewherein the n-type source and drain regions in the NMOS region andp-type source and drain regions in the PMOS region are substantiallyremoved therefrom. Another example comprises etching into thesemiconductor body in both the NMOS and PMOS regions to form recessessubstantially aligned to the gate structure wherein the n-type sourceand drain regions in the NMOS region and p-type source and drain regionsin the PMOS region are entirely removed therefrom. In one example, suchrecesses are formed immediately after gate patterning or after formationof offset spacers (used for extension region implants) on lateral edgesof the gate. The recesses are then filled with silicon germanium via aselective epitaxial deposition process. The silicon germanium materialhas a different lattice spacing than the silicon channel, therebyimparting a compressive strain to the channel region under the gate.

In one example, the silicon germanium material is doped with boronin-situ for the formation of p-type extension regions. In anotherexample, an extension region implant is performed into the silicongermanium material after the selective epi deposition, followed by theformation of sidewall spacers and source/drain implants. Having theboron doped silicon germanium material (either doped in-situ or viaimplantation) close to the gate as opposed to laterally spaced away(e.g., at the source/drain locations) advantageously allows lessgermanium to be employed in the recesses for a given desired stress,thereby reducing threading dislocation defects.

The following description and annexed drawings set forth in detailcertain illustrative aspects and implementations of the invention. Theseare indicative of but a few of the various ways in which the principlesof the invention may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart illustrating a method of forming a transistorhaving improved Tox according to one aspect of the present invention;

FIGS. 2A-2J are partial cross section diagrams illustrating varioussteps of forming NMOS and PMOS transistors in accordance with theinvention of FIG. 1;

FIG. 3 is a flow chart diagram illustrating a method of forming atransistor having improved Tox according to another aspect of thepresent invention;

FIGS. 4A-4F are partial cross section diagrams illustrating varioussteps of forming NMOS and PMOS transistors in accordance with theinvention of FIG. 3;

FIG. 5 is a flow chart diagram illustrating a method of forming atransistor having improved Tox according to yet another aspect of thepresent invention; and

FIGS. 6A-6C are partial cross section diagrams illustrating varioussteps of forming an NMOS transistor in accordance with the invention ofFIG. 5.

DETAILED DESCRIPTION OF THE INVENTION

One or more implementations of the present invention will now bedescribed with reference to the attached drawings, wherein likereference numerals are used to refer to like elements throughout, andwherein the illustrated structures are not necessarily drawn to scale.The invention provides transistor structures and methods in whichtransistor mobility is improved while minimizing defects heretoforeassociated with conventional strained silicon device solutions.

Referring now to FIGS. 1 and 2A-2J, further aspects of the inventionrelate to methods of fabricating integrated circuits, wherein FIG. 1illustrates an exemplary method 100 in accordance with the invention,and FIGS. 2A-2J illustrate the exemplary transistor device at variousstages of fabrication in accordance with the invention. While theexemplary method 100 is illustrated and described below as a series ofacts or events, it will be appreciated that the present invention is notlimited by the illustrated ordering of such acts or events. For example,some acts may occur in different orders and/or concurrently with otheracts or events apart from those illustrated and/or described herein, inaccordance with the invention. In addition, not all illustrated stepsmay be required to implement a methodology in accordance with thepresent invention. Furthermore, the methods according to the presentinvention may be implemented in association with the fabrication of ICsand composite transistors illustrated and described herein, as well asin association with other transistors and structures not illustrated,including but not limited to NMOS and/or PMOS composite transistors.

The method 100 begins at 102, wherein transistor fabrication isinitiated, and transistor well formation and isolation processing isperformed at 104. Act 104 thus defines NMOS and PMOS regions illustratedin FIG. 2A, wherein NMOS regions comprise a P-well 206 in which n-typesource/drain regions will later be formed, and PMOS regions comprise anN-well 208 in which p-type source/drain regions will later be formed,respectively. In addition, isolation regions may comprise shallow trenchisolation (STI) or field oxide regions (FOX) 210 that serve to definevarious active areas and electrically isolate various active areaslaterally from one another.

The method 100 continues at 106, wherein a gate oxide layer 212 isformed in active areas 211 defined by the various formed isolationregions 210. In one example, the gate oxide 212 comprises a thin,thermally grown silicon dioxide layer; however, other type gatedielectrics (such as high-k dielectrics) may be formed and arecontemplated by the present invention. A conductive gate layer 214 isthen deposited over the gate oxide 212 at 108 and patterned to form aconductive gate electrode 214. For example, a polysilicon layer may bedeposited via chemical vapor deposition (CVD) and patterned via etchingto form gate electrodes 214 in both the NMOS and the PMOS regions,respectively. At 110, a protective cap 218 is formed on top of the gateelectrode after etching and protects the gate electrode from asubsequent etch to remove the source/drain region, as discussed infra.The protective cap 218 comprises an insulating material such as anoxide, a nitride or a combination of such layers. For example, a nitridelayer is left remaining on top of the gate electrode.

An extension region implant 230, 236 is performed at 112. For example,lightly doped, medium doped or heavily doped extension region implantsare performed in the NMOS and PMOS regions, or alternatively, the NMOSregions and PMOS regions may be implanted separately with differingdopants by mask off each region, respectively. Alternatively, theextension region implants are formed after the offset spacer at 114,wherein both are self-aligned with respect to the offset spacer, therebyplacing both regions extremely close to the lateral edge of the gatestructure within the semiconductor body. A thermal process such as arapid thermal anneal is then employed to activate the extension regiondopants, which causes the extension regions to diffuse laterallyslightly underneath the offset spacer toward the channels.

An offset spacer 216 is formed on lateral edges of the conductive gateelectrodes at 114. For example, a thin offset layer (e.g., an oxide ornitride layer) is formed generally conformably over the patterned gateand then etched using a generally anisotropic dry etch to remove theoffset layer material on top of the gate and in the source/drainregions, leaving a thin offset spacer material on lateral edges of thegate. The offset spacer 216, as will be further appreciated below, isemployed in this example to isolate the strain inducing material awayfrom the channel region under the gate, for example, a distance of about5 nm to about 20 nm. For example a distance of 5 nm may be chosen inthis embodiment.

A first implant over the entire area of the gate structure and thesource/drain regions is performed at 116. In one example, the implant isdone with a high enough doping energy to penetrate through theprotective cap 218 overlying the gate structure. For example, in thisembodiment a doping energy of about 60 KeV can be used. In addition, theheavily doped ion concentration damages the silicon surrounding thesource/drain regions implanted and further allows easy removalafterwards. In one example, the implant is performed at an anglerelative to a plane normal to the surface. The source/drain implant issubstantially normal to the surface of the semiconductor body, however,in alternative embodiments, the source/drain implant may be performed atsome angle with respect to normal and such alternatives are contemplatedas falling within the scope of the present invention. In suchalternative embodiments, the angled implant is performed at a firstangle, while the source/drain implant is performed at a second angle,wherein the first angle is larger than the second angle, as measuredwith respect to the plane normal to the surface of the semiconductorbody.

Still referring to FIG. 1, the source/drain regions formed at 116 arespecifically etched to recess substantially all or most of the firstsource/drain implant at 118 in the source/drain region. In one example,the recess is about 200 angstroms or less for an optimal depth for whichto remove most of the first source/drain implant. In another example,the source/drain regions formed at 116 are etched to remove all of thefirst source/drain implant in that region. The protective cap 218remaining on the poly gate structure 214 during formation at 110protects the gate structure from being etched at 118 during removal ofthe source/drain regions. Therefore, the etch is selective to siliconversus the protective cap (a nitride, for example). The first implantdamage typically makes the silicon easy to etch, wherein the nitrideprotective cap is amorphous so its etch rate is not affected by theimplant.

Sidewall spacers can also be formed on the gate structures at 118. Thesidewall spacers comprise an insulating material such as an oxide, anitride or a combination of such layers. The spacers are formed bydepositing layer(s) of such spacer material(s) over the device in agenerally conformal manner, followed by an anisotropic etch thereof,thereby removing such spacer material(s) from the top of the gatestructure and from the moat or active area and leaving a region on thelateral edges of the gate structure, overlying the offset spacers. Thesidewall spacers 238 are thicker than the offset spacers, therebyresulting in the subsequently formed source/drain regions to be offsetfrom lateral edges of the gate structure 224 at least about 60 nm.

The protective cap 218 is removed at 120 and source/drain regions areformed again by a source/drain implantation at 122, wherein asource/drain dopant is introduced into the exposed areas (top of gateelectrode and active areas not covered by sidewall spacers). Theimplantation 122 is a doping concentration that is less than theimplantation at 116 to specifically target the source/drain regions thatwere previously removed. In one example, the source/drain region isextended a deeper than the recess depth to about 300 angstroms deep. Themethodology 100 therefore contemplates decoupling of the Tox versus SCEtradeoff so that an optimal amount of source/drain region is implantedwithout a harmful effect upon the gate electrode. The source/drainregions are completed with a thermal process to activate the dopant.

The method 100 concludes with silicide processing at 124, wherein ametal layer is formed over the device, followed by a thermal process,wherein the metal and silicon interfaces react to form a silicide (ontop of the gate and in the source/drain regions). Un-reacted metal isstripped away, and back end processing such as interlayer dielectric andmetallization layers are formed at 126 to conclude the device formationat 128. Stripping away un-reacted metal is a process well known by thoseof skill in the art.

The method 100 of the present invention advantageously minimizes theamount of leakage resulting from a non-optimal oxide thickness (Tox). Bydecoupling the implantation of the poly gate structure from theimplantation in the source/drain regions, an optimal amount of Toxwithout using additional masking can be obtained.

Turning now to FIGS. 2A-2J, partial cross section diagrams illustratinga transistor device being formed in accordance with the presentinvention of FIG. 1 are provided. In FIG. 2A, a transistor device 202 isprovided, wherein a semiconductor body 204, such as a substrate, has anumber of wells formed therein, such as a P-well 206 to define an NMOStransistor device region and an N-well 208 to define a PMOS transistordevice region, respectively. Further, isolation regions 210 such asfield oxide (FOX) or STI regions are formed in the semiconductor body todefine active area regions 211, as may be appreciated. In FIG. 2B, thetransistor device 202 is illustrated, wherein a gate dielectric 212 hasbeen formed, for example, thermally grown SiO₂, over the active areas211.

Referring to FIGS. 2C and 2D, a conductive gate electrode material(e.g., polysilicon) has been deposited and patterned via an etchingprocess 215 to form a gate electrode 214 overlying the gate oxide 212.On top of the gate electrode 214 remains a protective cap 218. Theprotective cap 218 is left on top of the gate electrode during etchingand protects the gate electrode from removal of the source/drainimplant, as discussed infra. The protective cap 218 comprises aninsulation material comprising an oxide, nitride or a combinationthereof. For example, a nitride protective cap may be present.

In addition, a thin offset spacer 216 in FIG. 2D, such as an oxide orother dielectric material may be formed on lateral sidewalls of the gatestructures 214 wherein the offset spacers have a width 216 a of about10-50 nm. The offset spacers 216 may be formed prior to the formation ofthe extension region or in another embodiment may be formed after theextension region formation. Alternatively, extensions regions maysubsequently be formed without any formation of spacers.

As illustrated in FIG. 2E, an implant 222 is illustrated generically toshow formation of extension regions 230, 236 in exposed active areas. Aswill be appreciated, however, the extension regions 230, 236 in the NMOSand PMOS regions are different and are performed separately with maskingsteps (not shown). For example, NMOS n-type extension regions 230 areformed with an n-type implant into the p-well 206 while the PMOS regionis covered with a mask. Similarly, PMOS p-type extension regions 236 areformed with a p-type implant into then n-well 208 while the NMOS regionis covered with a mask. Further, while a discussion of the formation ofthe extension regions is together, they may be formed at other times inthe fabrication process, and all such alternatives are contemplated asfalling with the scope of the invention.

Following the formation of the protective cap 218, a first source/drainimplant 228 is performed at FIG. 2F. The first source/drain implant 228is over the entire area of the gate structure and the source/drainregions. In one example, the implant is done with a doping energy highenough to penetrate through the protective cap overlying the gatestructure. For example, about 60 KeV can be used depending on thethickness of the protective cap. In addition, the high energy heavydoped concentration also damages the silicon surrounding thesource/drain regions implanted for their easy removal at another etch,as discussed infra. In one example, the implant is performed at anangle. The source/drain implant is substantially normal to the surfaceof the semiconductor body, however, in alternative embodiments, thesource/drain implant may be performed at some angle with respect tonormal and such alternatives are contemplated as falling within thescope of the present invention. In such alternative embodiments, theangled implant is performed at a first angle, while the source/drainimplant is performed at a second angle, wherein the first angle islarger than the second angle, as measured with respect to a plane normalto the surface of the semiconductor body.

In one example, an at least one angled first implant may be performed todope the gate structures 214. It should be understood that the angledfirst implant dopant is the same conductivity type as that employed forthe source/drain regions of the respective transistor device. That is,for an NMOS device the angled implant and source/drain implant are bothan n-type dopant. Similarly, for a PMOS type device both the angledimplant and the source/drain implant are p-type implants. Thisdistinguishes the angled implant of the present invention from aconventional halo or pocket implant that is employs an oppositeconductivity type dopant than used for the respective source/drain. Inone embodiment of the invention, the angle of the angled implant isabout 55 degrees or greater (measured from an angle normal to thesemiconductor body surface), wherein pocket or halo implants aretypically at an angle of about 20-30 degrees.

In addition, in one embodiment a relative dose of the angled implantcompared to conventional halo or pocket implants is greater by about twoorders of magnitude. In one embodiment, the angled implant of thepresent invention is about 1E15 to 4E15 ions/cm², for example about 2E15ions/cm² compared to a conventional halo or pocket implant of about 1E13to 8E13 ions/cm². Further still, the energies employed in the angledimplant of the present invention differ from the halo or pocket implantsdue to their desired function. For example, in one embodiment the angledimplant of the invention has a energy in the range of about 1-5 keV(depending on the dopant species), whereas a conventional halo or pocketimplant has an energy in the range of about 10-50 keV due to thediffering target depths of the implants. For p-type implants of boronthe energies are normally in the range of 5-15 keV, whereas for n-typeimplants of arsenic the energies are in the 35-60 kev range.

While an angled implant (not shown) may occur in both NMOS and PMOSregions concurrently, it should be noted that in one embodiment of theinvention, the angled implant comprises two angled implants, wherein ineach case one of the NMOS and PMOS regions is appropriately masked. Forexample, in one embodiment, the PMOS region is masked, and an n-typeangled implant is performed, thereby causing the n-type dopant toimplant into the NMOS region gate structures 214, while a shadowingstructures in the NMOS region may cause such dopant to not substantiallyreach the exposed active areas 211. Further, in performing an angledimplant in the PMOS region, the NMOS region is masked, and the dopant ofthe angled p-type implant reaches the PMOS gate structures, therebycausing such gate structures to be implanted with p-type dopant, whileany shadowing structures in the PMOS region cause such dopant to notsubstantially reach the exposed active areas 211.

Source/drain regions 220 and 224 are then formed in the NMOS and PMOSregions, respectively along with a doped region 226 below the protectivecap 218. In one example the source and drain regions 220 and 224 areformed in conjunction with the extension region implants. Thesource/drain implants 228 are performed with an NSD mask (not shown) andthen a PSD mask (not shown) in order to implant the NMOS region and thePMOS region separately with n-type and p-type dopant, respectively. Ascan be seen in FIG. 2F, the source/drain regions 220, 224 areself-aligned with respect to the sidewall spacers, and thus arelaterally spaced from the extension regions 230, 236.

In the above embodiment the source/drain implant is substantially normalto the surface of the semiconductor body, however, in alternativeembodiments, the source/drain and gate structure implant may beperformed at some angle with respect to normal and such alternatives arecontemplated as falling within the scope of the present invention. Insuch alternative embodiments, the angled implant is performed at a firstangle, while the source/drain implant is performed at a second angle,wherein the first angle is larger than the second angle, as measuredwith respect to a plane normal to the surface of the semiconductor body.

In one embodiment, illustrated in FIG. 2G, sidewall spacers 238 areformed. The sidewall spacers 238 comprise a dielectric material such asa silicon nitride and are formed by a substantially conformal depositionvia CVD, for example, followed by a substantially anisotropic etch(e.g., a dry etch) at 241. Resultant sidewall spacers are thus formed onlateral sidewalls of the gate structures 214, as illustrated in FIG. 2Gat 238. Further, while a discussion of the formation of the sidewallspacers are together, they may be formed at other times in thefabrication process, and all such alternatives are contemplated asfalling within the scope of the invention.

Recesses 248 are then formed at FIG. 2H in the source/drain regionsusing an etch process 243, wherein the gate electrode 214 is protectedby the protective cap 218. The recesses 248 are formed into thesemiconductor body to a depth 221 of about 10-90 nm, and more preferablyabout 30-70 nm, for example. In one example, all of the heavysource/drain implant 228 is removed by the subsequent etch 243. Inanother example, substantially all of the source/drain implant 228 isremoved. Although the example illustrated herein has the recesses 248formed after an offset spacer 216, such recesses may be formed prior tosuch a spacer, wherein in such instance the recesses 248 are aligned tothe lateral edges 214 a of the gate structures.

As illustrated in FIG. 21, the protective cap 218 is then removed. Asecond lighter implant dose 245 is then performed at the source/drainregions 220 and 224 to give the correct amount of doping for optimal Toxwithout compromising SCE. In one embodiment the source/drain implant issubstantially normal to the surface of the semiconductor body, however,in alternative embodiments, the source/drain implant may be performed atsome angle with respect to normal and such alternatives are contemplatedas falling within the scope of the present invention. In suchalternative embodiments, the angled implant is performed at a firstangle, while the source/drain implant is performed at a second angle,wherein the first angle is larger than the second angle, as measuredwith respect to a plane normal to the surface of the semiconductor body.

The method then concludes with silicidation, wherein a metal layer isdeposited, for example, via sputtering, over the device, followed by athermal process 246. During the thermal processing, those regions wherethe metal contacts silicon reacts to form a metal silicide 244, asillustrated in FIG. 2J. More particularly, the silicide 244 forms on thesource/drain regions and on top of the gates as illustrated.Subsequently, back end processing including metallization may beperformed to interconnect the various transistors, as may be desired.

In accordance with another aspect of the invention, FIG. 3 is a flowchart directed to another method of forming a transistor device havingimproved mobility due to a decoupling of the Tox-SCE tradeoff inherentin conventional methods and is designated at reference numeral 300. Themethod 300 is similar in many respects to the method 100 of FIG. 1, andwith regards to such aspects, those portions will not be repeated again.For example, acts 102-116 may proceed generally in the same manner asmethod 100. Recesses are then formed in the source/drain regions at 320after the entire structure comprising both the gate structure andsource/drain regions has been implanted with a heavy dose concentration.A silicon germanium material is then formed in the recesses at 320. Therecess is formed using, for example, a dry etching process such as thechemistry employed to etch STI trenches in the semiconductor body whenforming isolation regions. The recesses, in one example extend into thesemiconductor body to a depth of about 10-90 nm, and more preferablyabout 30-70 nm. In the present example, the gate structure is maskedduring the recess formation; therefore if the gate electrode is composedof polysilicon, the recess formation process will not result in a recessformed in a top portion of the gate electrode material.

The method 300 then continues at 322, wherein silicon germanium isformed in the recesses. In one example, the silicon germanium is formedvia a selective epitaxial deposition process such as an LPCVD (lowpressure chemical vapor deposition) process using dichlorosilane andgermane as the source gases. In one alternative of the presentinvention, the above reactants are employed to form SiGe in the recessesand subsequently the SiGe is subjected to a p-type implant to form ap-doped SiGe material (e.g., using Boron). Alternatively, and morepreferably, the SiGe is doped in-situ during the selective epideposition process by incorporating a p-type dopant reactant in the CVDprocess. For example, diborane or other type reactant may be employed,wherein a boron doped SiGe material is formed in the recesses (or otherp-type dopant in the SiGe, as may be appreciated). The in-situ borondoping of the SiGe is preferred because it is believed that the in-situdoped boron is activated to a higher degree than when implanted into theSiGe, and therefore advantageously provides a lower extension regionresistance.

While not intending to be limited to any one theory, it is believed thatthe silicon germanium within the recesses form an alloy that has alattice with the same structure as the silicon body lattice, however,the silicon germanium has a larger spacing. Consequently, it is believedthat the silicon germanium within the recesses will tend to expand,thereby creating a compressive stress within the channel of thesemiconductor body underneath the channel.

If the SiGe material is not doped in-situ as, an extension regionimplant is subsequently performed, wherein dopants are introduced intothe silicon germanium material in the recesses. For example, lightlydoped, medium doped or heavily doped extension region implants areperformed in the NMOS and PMOS regions, or alternatively, the NMOSregions and PMOS regions may be implanted separately with differingdopants by mask off each region, respectively. Since both the recesses(now filled with silicon germanium) and the extension region implantsare formed after the offset spacer, both are self-aligned with respectto the offset spacer, thereby placing both regions extremely close tothe lateral edge of the gate structure within the semiconductor body. Athermal process such as a rapid thermal anneal is then employed toactivate the extension region dopants, which causes the extensionregions to diffuse laterally slightly underneath the offset spacertoward the channels.

The method 300 may then proceed at 124-128 in a manner similar to thatof method 100. Consequently, the method 300 indicates that the order inwhich the extension regions are formed and the recesses are formed maybe switched, and either alternative is contemplated as falling withinthe scope of the present invention.

The method 100 of the present invention advantageously minimizes theamount of leakage resulting from a non-optimal oxide thickness (Tox). Bydecoupling the implantation of the poly gate structure from theimplantation in the source/drain regions, an optimal amount of Toxwithout using additional masking can be obtained.

Having the silicon germanium region at the optimal depth in the activeregion and decoupled from the implantation of the gate structureprovides for a substantial improvement over the prior art in that thereis substantially less degradation of the gate structure duringfabrication and an optimal current flow without punchthrough may beobtained. Consequently, less germanium is needed and few threadingdislocation defects are generated, thereby resulting in substantialperformance improvements over the prior art, for example, reducedleakage. In addition, in the instance where the SiGe material is dopedin-situ with boron, it was found that the extension region resistancewas decreased. Accordingly, with an approximate 35% PMOS deviceimprovement, it was estimated that about 28% of the improvement is fromimproved stress, while about 7% is due to the extension regionresistance improvement.

FIGS. 4A-4F illustrate the fabrication of the transistor devices inaccordance with the method 300 of FIG. 3. As illustrated in FIG. 4A, atransistor device has NMOS and PMOS regions as before with P-well andN-well regions 206 and 208 formed in a semiconductor body 204. Isolationregions 210 also are provided to define active areas for fabrication oftransistor devices. A gate oxide 212 overlies the active regions and apatterned conductive gate electrode 214 is formed thereover. A nitridecap 218 remains over top of the gate electrode 214 at 110. In contrastto the method 100, the protective nitride cap 218 remains on top of thegate electrode and is not etched prior to any subsequent implant in themethod 300. Offset spacers 216 reside on lateral edges of the gate 214and an extension region implant process 404 (e.g., an n-type followed bya p-type) is provided in conjunction with appropriate masking to formextension regions 230 and 236, respectively. A subsequent thermal annealcauses the extension regions 230 and 236 to diffuse laterally and extendslightly under the offset spacers 216.

FIGS. 4B-4D progress similarly to that described in the previous method,wherein sidewall spacers 238 are formed, followed by the source/drainimplant 406 at FIG. 4B (in NMOS regions and then PMOS regions,respectively with appropriate masking not shown) and wherein at leastone angled implant may be formed. Note that after the source/drainimplants 220 and 224, a thermal process is employed to activate thedopants, which causes some lateral diffusion thereof, thereby causingthe source/drain regions to connect with the respective extensionregions 230 and 236.

Recesses 248 are then formed in the active areas after the extensionregion implant via an etch process 408, as illustrated in FIG. 4D.Because the extension regions have diffused slightly under the offsetspacers 216 and the recesses are self-aligned with respect to thespacers, small portions of the extension regions remain near thechannel, as illustrated. A silicon germanium material 450 is then formedin the recesses as illustrated in FIG. 4E, via a selective epitaxialdeposition process 410. Although the example illustrated herein has therecesses 248 formed after an offset spacer 216, such recesses may beformed prior to such a spacer, wherein in such instance the recesses 248are aligned to the lateral edges 214 a of the gate structures.

Turning now to FIG. 4E, a selective epitaxial deposition process 410 isprovided, wherein a silicon germanium material 450 is formed in therecesses 248. As highlighted above, the process may comprise anepitaxial deposition process, wherein a germanium containing source gassuch as germane is added to the silane or dichlorosilane, such that asilicon germanium material is formed in the recesses. Further, in oneexample, the selective epi process further includes a diborane sourcegas to provide for the SiGe to be doped with boron in-situ.Alternatively, other p-type source gases may be employed, as may beappreciated.

Alternatively, the SiGe material may be formed in the recesses 248.Alternatively in one example (not shown), the SiGe may alternatively besubsequently doped with a p-type dopant to form a p-type extensionregion in the PMOS region if an extension region had not previously beenformed. In such case, the PMOS region is then masked off with a maskingmaterial such as photoresist, and an extension region implant 230 isperformed to form n-type extension regions 230 in the NMOS region. Ifthe SiGe material is p-type doped in-situ, the n-type extension regioncan be made greater to offset such p-type dopant therein, as may beappreciated. A thermal process such as a rapid thermal anneal is thenperformed to activate the dopant, wherein a lateral diffusion of theextension regions 230 under the offset spacer 216 is achieved.

The p-type extension region mask is then removed, and a n-type extensionregion mask is deposited and patterned to cover the NMOS region. Ap-type extension region implant process is then performed to form p-typeextension regions 236 in the PMOS region, as illustrated. As statedabove, if the SiGe is formed with p-type doping in-situ, the p-typeextension region masking and implant may be skipped.

FIG. 4F then progresses similarly to that described in the previousmethod, wherein silicidation occurs for subsequent metallization andback end processing.

In the methods of FIG. 3, the recesses and a SiGe selective epitaxialprocess are performed in both the NMOS and the PMOS regions. Theinventors of the present invention discovered that although thecompressive stress provided by the SiGe effectively improves holemobility substantially for PMOS performance improvement, that thepresence of germanium in the NMOS regions may, in some instances, have asubstantial deleterious impact on electron mobility in the NMOS regions.Accordingly, the present invention contemplates another alternativeaspect of the present invention, wherein the recesses and fillingthereof with boron doped silicon germanium material may be performedsolely in the PMOS regions of the device, as will be discussed below andillustrated in conjunction with FIGS. 5 and 6A-6C.

Turning now to FIG. 5, a method 500 is disclosed wherein a PMOStransistor is formed in a CMOS process that exhibits improved Tox usingSi recessing without the use of additional mask. Acts 102-110 mayproceed in a manner similar to that discussed supra, with a protectivecap comprising an oxide, nitride, or combination thereof remaining ontop of the gate structure. At 502, a mask is deposited and patterned tocover the NMOS region and a p-type source/drain implant is performedtherein to form p-type source/drain regions that are self aligned withrespect to the spacers and also implant the gate structure through theprotective cap 218. The implant dose concentration is strong enough topenetrate through the protective cap to implant the gate structure. Themask is then removed and a second mask is provided to cover the PMOSregions, and an n-type source/drain implant is performed at 504 in theNMOS regions to form n-type source/drain regions therein that areself-aligned with respect to the spacers and implant the gate structureas well.

At 506, a moat recess is selectively formed in an N-well (a PMOS region)by masking off the P-well (the NMOS region) and performing a siliconetch after the formation of offset spacers on the sidewalls of the gateelectrodes. Boron or other p-type doped silicon germanium is formed inthe recesses (in the active areas as well as on top of the gateelectrode) via a selective epi deposition process in the PMOS region at508 while the mask is maintained on the NMOS region, thereby preventingsuch material to form therein.

If the SiGe is not p-doped during selective epi deposition, p-typeextension regions are then formed at 510 with the mask still in place,thereby doping the silicon germanium material within the recesses withp-type dopants, if desired. A thermal process then causes the p-typedopant to diffuse laterally under the offset spacers, and toward thechannel. Alternatively, the p-type extension regions may be formed priorto forming the recesses.

The method 500 continues at 512 by removing the mask in the NMOS region,depositing and patterning another mask over the PMOS region, andperforming an n-type extension region implant into the P-well in theNMOS region to form n-type extension regions that are self-aligned withrespect to the offset spacers. The mask is then removed. Silicideprocessing 122 and back end processing 124 may then proceed in a typicalmanner.

In FIG. 6A, the device 602 is illustrated with a mask 604 over the NMOSregion and a nitride cap 218 over the gate structure 214. A p-typesource/drain implant 606 is performed in the PMOS region to form thesource/drain regions 224. The mask 604 is then stripped, and anothermask 614 is formed to cover the PMOS region, and an n-type source/drainimplant process 624 is provided to form n-type source/drain regions 220,as illustrated in FIG. 6C.

In FIG. 6B, an etch process 610 is performed to form the recesses 608 inthe active areas defined by the offset spacers 216 and the isolationregions 210. In FIG. 6C, a selective epitaxial deposition process 612 isperformed, wherein a silicon germanium material 650 is formed in therecesses 608 while the mask 604 continues to mask the NMOS region. Inone example, the selective epi process 612 further includes a p-typedopant such as boron, wherein the resultant material comprises borondoped silicon germanium 650. Alternatively, the PMOS region is thensubjected to a p-type extension region implant 612, wherein the p-typeextension regions 236 are formed (FIG. 6C) into the SiGe material 650. Asubsequent thermal anneal causes the extension regions to diffuselaterally slightly under the offset spacers. he mask 604 is thenremoved, and another mask 614 is formed and patterned to overlie thePMOS region (not shown). An n-type extension region implant is thenperformed to form n-type extension regions in the NMOS region.

In the above manner, the device may be fabricated with optimized PMOStransistors without any strain applied to the channel in NMOS devices.In addition, while the invention is described above with respect to theuse of germanium to form a silicon germanium lattice structure, thepresent invention contemplates the use of any element that will createan alloy with silicon and serve to impart a compressive stress to thechannel of the PMOS devices, and such alternatives are contemplated asfalling within the scope of the present invention.

While the invention has been illustrated and described with respect toone or more implementations, alterations and/or modifications may bemade to the illustrated examples without departing from the spirit andscope of the appended claims. In particular regard to the variousfunctions performed by the above described components or structures(assemblies, devices, circuits, systems, etc.), the terms (including areference to a “means”) used to describe such components are intended tocorrespond, unless otherwise indicated, to any component or structurewhich performs the specified function of the described component (e.g.,that is functionally equivalent), even though not structurallyequivalent to the disclosed structure which performs the function in theherein illustrated exemplary implementations of the invention. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application. Furthermore, to the extent that the terms“including”, “includes”, “having”, “has”, “with”, or variants thereofare used in either the detailed description and the claims, such termsare intended to be inclusive in a manner similar to the term“comprising”.

1. A method of forming a transistor device, comprising: forming a gatestructure over a semiconductor body of a first conductivity type whereinthe gate structure comprises a protective cap thereover and definessource/drain regions laterally adjacent thereto; performing a firstimplant of a second conductivity type into the gate structure thru theprotective cap and into source/drain regions; etching into thesemiconductor body to form recesses substantially aligned to the gatestructure wherein dopant of the first implant is substantially removedfrom the source/drain regions; removing the protective cap; andperforming a second implant of the second conductivity type into thesource/drain regions and the gate structure.
 2. The method of claim 1,wherein forming the gate structure comprises: forming a gate oxide overthe semiconductor body; and depositing and patterning a conductive layerto form a gate electrode over the gate oxide.
 3. The method of claim 1,further comprising: forming extension regions of the second conductivitytype adjacent to the gate structure, wherein performing the firstimplant is distinct from forming said extension regions; and formingsidewall spacers adjacent to the gate structure.
 4. The method of claim1, wherein the second implant is a lesser energy dose implant than thefirst implant dose and wherein the first implant dose is a high energydose compared to the second implant.
 5. The method of claim 1, whereinthe first implant and the second implant comprise performing at leastone angled implant.
 6. The method of claim 1, wherein the recesses areless than about 200 angstroms in depth.
 7. The method of claim 1,wherein the protective cap comprises a nitride and wherein etching intothe semiconductor body to form recesses removes all of the firstsource/drain implant.
 8. A method of forming a transistor device,comprising: forming a gate structure over a semiconductor body of afirst conductivity type wherein the gate structure comprises aprotective cap thereover and defines source/drain regions laterallyadjacent thereto; performing a source/drain implant of a secondconductivity type into the gate structure thru the protective cap andinto the source/drain regions; and etching into the semiconductor bodyto form recesses substantially aligned to the gate structure whereindopant of the source/drain implant is substantially removed therefrom;performing a selective epitaxial growth in the recesses.
 9. The methodof claim 8, wherein performing the selective epitaxial growth furthercomprises a deposition of silicon germanium in the presence of a borondopant containing source gas, wherein the boron dopant dopes theepitaxially grown silicon germanium in-situ.
 10. The method of claim 8,wherein performing the selective epitaxial growth comprises growing aboron doped silicon germanium in the recesses.
 11. The method of claim1, further comprising forming sidewall spacers on the lateral edges ofthe gate structure before forming the recesses, wherein the recesses arealigned in the semiconductor body with respect to offset spacers. 12.The method of claim 8, wherein the source/drain implant furthercomprises performing at least one angled implant, wherein the at leastone angled implant results in doping contacting a top portion of thegate structure.
 13. The method of claim 8, wherein the firstconductivity type is n-type and the second conductivity type is p-type.14. The method of claim 8, wherein the source/drain implant is a doseconcentration in the range of about 1E15 to 4E15 ions/cm² and whereinetching into the semiconductor body to form recess removes all of thesource/drain implant.
 15. The method of claim 1, further comprising:forming extension regions of a second conductivity type adjacent to thegate structure.